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Showing results for tags 'OC2'.
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This is something that I'm scratching my head over. It would be great if this were written in C (and if I had a dollar for every time I thought that... I think I'm up to about $5 now?), but alas, it isn't, and thus multiple return values are very much out of the question. Having a think about it, it would make sense if the bus ran at 1MHz. The Z80 currently runs at 2MHz, and all memory accesses on the Z80 tend to take a minimum of 3 cycles (in reality it's more like 2 cycles followed by a DRAM refresh but we'll just skip on that and assume the whole window is available for it). The MIPS3 core -
Draft 1 D1: 2016-08-05T02:45:39+00:00 $ date -u -Iseconds ----There are two address spaces for all components: the config space, and the main I/O space. Every component has a VID (virtual ID) and that is how components are addressed. Every VID should be physically settable to any 8-bit value on each component. Any component with a VID set to 0xFF is rendered inaccessible by any methods that address by VID. Every component also has a PID (physical ID) which indicates the physical location of this component on a given bus master. The config space is read-only. Everything in the confi